As integrated circuits are further reduced in process-dimension towards very deep sub-micron (VDSM) level or even nanometer level, the density of power consumption on chip unit area increases exponentially, making power consumption an important issue which is an inevitable consideration in integrated circuit design, besides circuit performance Especially, in recent years, various systems on chip (SoC), such as battery-powered hand-held devices and wireless sensor network node chips, etc., has increasingly high demand for power consumption; therefore, how to minimize the power consumption of chips has become a key in the field of integrated circuit design.
In existing low-power consumption chips, the dynamic power consumption of chip is effectively reduced by the dynamic voltage scaling method according to the performance requirement and power consumption level of SoC; however, the conventional low-power consumption applications oriented dynamic voltage scaling technique employs an open loop system, which determines the value of VDD by looking up in a pre-established relational table of supply voltage VDD vs. operating frequency f of the SoC, and can't make quick and accurate response to the real-time operating condition of the SoC; therefore, the regulation has some drawbacks such as blindness, poor control and low accuracy, etc.
The on-chip monitoring method monitors the working condition of the circuit in real time by inserting on-chip monitoring circuits to the terminals of critical paths in the main circuit of the SoC, and attributes the impacts of process variation, power supply voltage fluctuation, temperature variation, and noise, etc. on the circuit to the variations of time-delay characteristics of the on-chip monitoring circuits in the critical paths. Once timing violation occurs in the circuit, the on-chip monitoring circuit will create a corresponding error signal, which will be used as the scaling basis for a supply voltage scaling module.
The schematic diagram of dynamic voltage scaling based on on-chip monitoring circuits is shown in FIG. 1. This method can monitor the error level of the main circuit in real time during operation, and reflect the actual impact of global and local disturbances on the circuit; by introducing an error detection and correction mechanism, the voltage margin reserved in the main circuit design stage against adverse factors such as process variation, power supply voltage fluctuation, temperature variation, and noise, etc. can be further released, so that the chip will operate at the allowable minimum supply voltage, and therefore the power consumption will be optimized.
In practice, voltage converters (e.g., DC-DC, LDO) are usually required for supply voltage scaling, and these devices take some time in themselves during voltage scaling, which means the voltage scaling has a hysteretic nature. This problem is not taken into account in the conventional voltage scaling method. As a result, when the voltage scaling is completed, the working environment and state of the circuit may have been changed, and at this time the regulated voltage can't meet the operating demand of the circuit currently. Therefore, an appropriate mechanism is required to predict the variation trend of the operating voltage of the circuit, so as to guide the voltage converters for voltage scaling and reserve some time for voltage conversion in the converters, and thereby adapt to the circuit variations in a better way.
The prediction object of the Markov chain is a dynamic system with random variations, and its prediction is to speculate the future developing trend of a system according to the state transition probability between states. The Markov process requires that the states don't have after-effect. The internal working environment of a chip is subject to the impact of temperature, process variation, and noise, etc.; all of these are random variables, and the instruction executed by the circuit at a specific moment has a certain randomness. Therefore, the process that the on-chip monitoring circuit monitors the circuit error probability in a fixed time period is a random process. Since the current state of a circuit is the accumulative of the “past” and the future variation depends on the “current” condition instead of the past condition, therefore the random process meets the characteristics of Markov process.